Superconducting Platform Technologies

What is this call about?

The call funds the construction and demonstration of a modular, full-stack superconducting quantum computer aiming at 1,000 physical qubits, integrated with HPC and accessible via the cloud. One project is expected to be funded.

What does this call fund?

Scope

The action supports the scale-up and practical deployment of superconducting quantum computing platforms in Europe. Proposals must tackle at least two of the critical technical roadblocks identified in the SRIA 2030, and these must include error correction and fault tolerance, and cryogenic and interconnect engineering at the scale of 1,000 or more qubits.

Expected outcomes

• A full-stack superconducting quantum computer aiming at 1,000 physical qubits, with a chiplet-based QPU architecture that is scalable and user-adjustable.
• Target performance: T1 coherence time above 100 microseconds, one- and two-qubit gate and read-out fidelities of at least 99.9%, read-out speed below 300 ns and two-qubit gate speed below 20 ns.
• Quantum advantage demonstrated on selected industrial use cases and benchmarked against best-in-class classical methods.
• A cloud-accessible system integrated with high-performance computing environments, and a standardised software stack for bring-up, calibration, control, benchmarking and user access.
• Stronger European supply chains and industrial capacity for superconducting quantum technologies.

Activities

• Build a modular machine integrating quantum hardware, cryogenic infrastructure, control electronics and software.
• Set up test capacity at production sites, including cryogenic screening of chiplets before assembly, and interoperability and open standards across chiplet manufacturers, together with standards and EU-wide certification schemes.
• Develop and validate error correction and fault-tolerance schemes for superconducting qubits.
• Demonstrate at least two real-life industrial use cases during the project.
• Provide standardised interfaces for hybrid workflows with classical HPC and cloud platforms, remote access for academic, research and industrial users, and open access for co-design, with training and documentation.

Technology readiness

Activities are expected to start at TRL 4 and reach TRL 7 by the end of the project.

When is the deadline?

17 November 2026 (12 days)